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ISL6244EVAL1 Multi-phase Evaluation Board Setup Procedure
Application Note September 2003 AN1077
This document describes the setup procedure for the ISL6244EVAL1 Rev B board for AMD Mobile K8 Processors.
Features
* Multi-Phase Power Conversion - 2, 3 or 4 Phase Operation * Precision rDS(ON) Current Sharing - Lossless - Low Cost * Precision CORE Voltage Regulation - Differential Remote Output Voltage Sensing - Programmable Reference Offset - 1% System Accuracy * Programmable Droop Voltage * Excellent Dynamic Response - Combined Input Voltage Feed-Forward and Pulse-byPulse Average Current Mode
Description
The AMD Hammer family microprocessors feature higher clock speeds and greater device density than previous product families. The power management solution for this next generation family of microprocessors must contend with lower core voltages, tighter transient specifications, and higher peak current demands. Responding to the changing power management needs of its customers, Intersil introduces the ISL6244 controller to power the AMD Hammer family microprocessors.
Intersil ISL6244 and ISL6207
The ISL6244EVAL1 Rev B is a versatile voltage regulatordown (VRD) design. The evaluation board comes configured for 3-phase multi-phase buck operation, designed to meet AMD Hammer Family Desktop Processor specifications. The board layout supports removal or addition of the third and fourth phases to support multiple applications. The ISL6244 controller features are specifically designed to compliment and support the Hammer Family processors. Interfaced with ISL6207 drivers, the chipset forms a highly integrated solution for AMD Hammer processor applications. The ISL6244 regulates output voltage and balances load currents for two to four synchronous buck converter channels. The controller features a 5-bit DAC which provides a digital interface for accurate step down conversion over the entire Hammer Family range of 0.800V to 1.550V. New multi-phase family features include differential remote output voltage sensing to improve regulation tolerance, pinadjustable reference offset for ease of implementation, VIDon-the-Fly to respond to DAC changes during operation, and optional load line regulation. For a more detailed description of the ISL6244 functionality, refer to the data sheet [1]. The ISL6207 driver is chosen to drive two N-Channel power MOSFETs in a synchronous-rectified buck converter channel. Each channel has a single logic input which controls the upper and lower MOSFETs. Dead time is optimized on both switching edges to provide shoot-thru protection. Internal bootstrap circuitry only requires an external capacitor and provides better enhancement of the upper MOSFET. For a more detailed description of the ISL6207, refer to the data sheet [1]. The Intersil multi-phase family driver portfolio continues to expand with new selections to better fit our customer's needs.
1. Refer to our website for updated information, the ISL6207 data sheet, and the ISL6244 data sheet: www.intersil.com.
Ordering Information
PART NUMBER TEMP. (oC) ISL6244CR ISL6244CRZ ISL6244HR ISL6244HRZ 0 to 70 0 to 70 PACKAGE 32 Ld QFN 32 Lead-Free QFN PKG. DWG. # L32.5X5 L32.5X5 L32.5X5 L32.5X5
-10 to 100 32 Ld QFN -10 to 100 32 Lead-Free QFN
NOTE: Add "-T" suffix for 32 QFN 5x5 Tape and Reel packages.
Pinout
ISL6244CR (32 LEAD QFN 5X5) TOP VIEW
VFF EN PGOOD 25 24 PWM4 23 ISEN4 22 ISEN1 21 PWM1 20 PWM2 19 GND 18 ISEN2 17 ISEN3 9 IOUT 10 VDIFF 11 VSEN 12 RGND 13 GND 14 GND 15 VCC 16 PWM3 VID3 VID4 GND NC
32 VID2 VID1 VID0 NC OFS COMP FB NC 1 2 3 4 5 6 7 8
31
30
29
28
27
26
NC = NO CONNECT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
FS
Application Note 1077 What's Inside
The Evaluation Board Kit contains the following materials: * The ISL6244 EVAL Board * The ISL6244 Evaluation Board document Step 6: Step 5: Set the 0-12V power supply to +12V and place in the "STANDBY" or "OFF" position. Connect the positive terminal (+) of the supply to the +12V terminal J6 and the negative terminal (-) of the supply to GND J8. Connect the positive terminal (+) of a DMM to the +5V terminal J5 and the negative terminal (-) to the GND terminal J7. Connect the positive terminal (+) of the electronic load to the VOUT terminal J1. Connect the negative terminal (-) of the electronic load to the GND terminal J2. Make sure the electronic load is set to the 0A condition. Connect the positive terminal (+) of a DMM to the VOUT test point TP13 and the negative terminal (-) to the GND test point TP14. Check to ensure all jumpers and switches are in their default positions prior to application of power (refer to"Detailed Description of Jumper Settings" and "Detailed Description of Switch Settings" ). Set all power supplies to the "ON" position. LED CR1 should show Red. Check all DMM displays for correct voltage levels. Adjust if necessary. Turn the ENABLE switch SW2 to the "ON" position. LED CR1 should show Green. The VOUT DMM should read 1.60V (1%).
What is Needed
The following materials will be needed to perform testing: * 1 to 2 electronic loads [see note] - 0-25V @ 15A (+VDC) - 0-5V @ 5A (+5V) - 0-12V @ 1A (+12V) * precision digital multi-meters
NOTE: amperage rating of power supplies are determined by maximum expected loading plus a percentage margin of error
Step 7:
Step 8:
Step 9:
Quick Setup Guide
Step 1: Set the 0-5V power supply to +5V and place in the "STANDBY" or "OFF" position. Connect the positive terminal (+) of the supply to the +5V terminal J5 and the negative terminal (-) of the supply to GND J7. Connect the positive terminal (+) of a DMM to the +5V terminal J5 and the negative terminal (-) to the GND terminal J7. Set the +VDC power supply to +19V and place in the "STANDBY" or "OFF" position. Connect the positive terminal (+) of the supply to the +VDC terminal J3 and the negative terminal (-) of the supply to GND J4.Connect the load Connect the positive terminal (+) of a DMM to the +VDC terminal J3 and the negative terminal (-) to the GND terminal J4. Step 10:
Step 11:
Step 2:
Step 3:
At this point the board has been properly powered up. Normal testing can begin.
NOTE: If you need technical assistance, or other assistance, with the ISL6244 Evaluation Board, call 1-888-INTERSIL (468-3774).
Detailed Description of Jumper Settings
JUMPER JP1 POSITION Shunted FUNCTION Berg Jumper for VCORE Set Point
Step 4:
Detailed Description of Switch Settings
JUMPER SW1 POSITION On Off (default) SW2 On Off(default) FUNCTION ENABLE On-Board Load Transient DISABLE On-Board Load Transient ENABLE ISL6244 and ISL6207 DISABLE ISL6244 and ISL6207
2
Application Note 1077
SW2 (ENABLE SWITCH) = OFF
ISL6244 CONTROLLER
JP1 5 BIT VID JUMPERS = SHUNTED
SW1 (LOAD TRANSIENT SWITCH) = OFF
FIGURE 1. ISL6244 EVAL BOARD INITIAL JUMPER AND SWITCH SETTINGS
3
Application Note 1077
+5V VCC INPUT SOURCE SPECTRUM ANALYZER INPUT FOR LOOP GAIN/PHASE MEASUREMENT
GND VCC INPUT RETURN
J3 +VDC
J4 GND
TEST POINT FOR ENABLE SENSE
TEST POINT FOR PGOOD SENSE
SCOPE JACK FOR PHASE2 MONITORING
SCOPE JACK FOR PHASE4 MONITORING
TEST POINT FOR PWM1 TEST POINT FOR PWM1 TEST POINT FOR PWM2 SCOPE JACK FOR PHASE4 MONITORING TEST POINT FOR PWM2
SCOPE JACK FOR PHASE3 MONITORING
TEST POINT FOR VCORE REMOTE SENSE
TEST POINT FOR VCORE REMOTE SENSE SCOPE JACK FOR ON-BOARD LOAD TRANSIENT CURRENT MEASUREMENT
SCOPE JACK FOR VOUT MONITORING
- NEGATIVE CONNECTION FOR ELECTRONIC LOAD
+ POSITIVE CONNECTION FOR ELECTRONIC LOAD
J6 +12V INPUT SOURCE
J8 +12V INPUT RETURN
FIGURE 2. ISL6244 EVAL BOARD TEST POINTS
4
Board Layout Information
5 4 3 2 1
+VDC R1 90K
+5V
D
R2 10K
C1 0.1uF R36 10k
D
1 1
C
32 31 30 29 28 27 26 25
VID3 NC VID4 VFF GND EN FS PGOOD
1
0
U1 ISL6244CR
1
33
B
PAD
IOUT 9 10 VDIFF 11 VSEN 12 RGND GND 13 GND 14 VCC 15 16 PWM3
1
1
12nF
2.43k C3 R8
715 C4 TP7
20.0 TP8 VCORE+ VCORER9
1
5
0
TP1 ENABLE PGOOD TP2 R41 0.0 R42 PWM4 ISEN4 ISEN1 PWM1 nopop R3 107k
0
Application Note 1077
C
TP3 PWM4 ISEN4 ISEN1 PWM1 PWM2 GND ISEN2 ISEN3
R4 2.5k
VID4 VID3 VID2 VID1 VID0
1 2 3 4 5 6 7 8
VID2 VID1 VID0 NC OFS COMP FB NC
24 23 22 21 20 19 18 17
Use to switch between 3 & 4-phase operation: 4-phase: pop R42 (0-ohm) nopop R41 3-phase: nopop R42 pop R41 (0-ohm)
B
TP5 1 TP4 PWM2 ISEN2 ISEN3 PWM3
R35
0
0.0 C2 R5 R6 R7
TP6
+5V
nopop
A
603
6.8nF
C5 1uF
10.0
Steve Laur
4020 Stirrup Creek Drive Durham, NC 27703 Size A Date: Title ISL6244 EVAL 1 for AMD Hammer Tuesday, June 17, 2003
2
A
0
Rev B 1
1
Sheet
of
5
5
4
3
FIGURE 3. SCHEMATIC 1
Board Layout Information (Continued)
5 4 3 2 1
+VDC +5V R10
0.0
D
PHASE1 Q1 Q2 - nopop TP9
D
C6 0.1uF U2 1 2 3 4 UGATE PHASE BOOT EN PWM VCC GND LGATE ISL6207 8 7 6 5 C7 1uF
0
L1 1
0.56uH 2 3
VOUT
6
C B A
PWM1 R37 nopop
Q3
Q4
0 0
R11 ISEN1 820PTC ENABLE R12
0 0
+5V +VDC
C
Application Note 1077
0.0 PHASE2 Q5 C8 0.1uF U3 1 2 3 4 UGATE PHASE BOOT EN PWM VCC GND LGATE ISL6207 8 7 6 5 Q6 - nopop TP10
0
L2 1
0.56uH 2 3
B
PWM2 R38 nopop
Q7 C9 1uF
Q8
0 0
R13 ISEN2 820PTC
0
0
Steve Laur
4020 Stirrup Creek Drive Durham, NC 27703 Size A Date:
5 4 3 2
A
Title ISL6244 EVAL 1 for AMD Hammer Wednesday, June 11, 2003 Sheet 2
1
Rev B of 5
FIGURE 4. SCHEMATIC 2
Board Layout Information (Continued)
5 4 3 2 1
+VDC +5V R14 PHASE3 0.0
D
Q9 C10 0.1uF U4 1 2 3 4 UGATE PHASE BOOT EN PWM VCC GND LGATE ISL6207 8 7 6 5 C11 1uF
Q10 - nopop
TP11
D
0
L3 1
0.56uH 2 3
VOUT
7
PWM3 R39 nopop
Q11
Q12
0 0
R15
C
0 0
ISEN3 820PTC ENABLE R16 +5V
Application Note 1077
C
+VDC
0.0 Q13 C12 0.1uF U5
B
PHASE4 TP12 Q14 - nopop
0
1 2 3 4 UGATE PHASE BOOT EN PWM VCC GND LGATE ISL6207 8 7 6 5 L4 1 0.56uH 2 3 Q15 C13 1uF Q16
B
PWM4 R40 nopop
0 0
R17 ISEN4 nopop
0
0
A
Use to switch between 3 & 4-phase operation: 4-phase: pop R17 (820-PTC) 3-phase: nopop R17
5 4 3
Steve Laur
4020 Stirrup Creek Drive Durham, NC 27703 Size A Date:
2
A
Title ISL6244 EVAL 1 for AMD Hammer Tuesday, June 17, 2003 Sheet 3
1
Rev B of 5
FIGURE 5. SCHEMATIC 3
Board Layout Information (Continued)
5 4 3 2 1
TP13 VOUT C14 nopop C15 nopop C16 nopop C17 nopop C18 nopop C19 330uF C20 330uF C21 330uF C22 330uF C23 330uF C24 330uF C25 nopop C26 nopop C27 nopop C28 nopop 1 C29 nopop
D
D
C30 22uF
C31 22uF
C32 nopop
C33 nopop
C34 22uF
C35 22uF
C36 22uF
C37 22uF
C38 22uF
C39 22uF
Output Capacitance
C40 22uF C41 22uF C42 nopop C43 nopop C44 22uF C45 22uF TP14 1
J1 VOUT
8
0
J2 GND
C
C
Application Note 1077
+VDC J3 +VDC2 C46 10uF C47 10uF C48 10uF C49 10uF C50 10uF
Input Capacitance
J4 GND
B
C51 10uF
C52 10uF
C53 10uF
C54 10uF
C65 10uF
C66 10uF
C67 10uF
B
0
J5 +5V +5V
J6 +12V +12V
+5V decoupling
(locate by power terminals)
A
+12V decoupling
(locate by power terminals)
C57 10uF C58 1uF J8
C55 10uF
C56 1uF
J7
Steve Laur
4020 Stirrup Creek Drive Durham, NC 27703
A
0
GND
0
GND Size A Date:
3 2
Title ISL6244 EVAL 1 for AMD Hammer Monday, July 14, 2003 Sheet 4
1
Rev B of 5
5
4
FIGURE 6. SCHEMATIC 4
Application Note 1077 Board Layout Information (Continued)
5 4
VCC_CORE TP15
Transient Load Generator
+12V
VOUT
U6 1 2 3 4 VDD HB HO HS HIP2100 C62 1uF 0 0 0 LO VSS LI HI 8 7 6 5
R18 357_1%
D1 1
C59 no pop
C60 no pop
C61 no pop
D
R20 357_1%
D2 1
+12V
3
R21 324_1%
2
Q18 HUF76129D3S
3
R19 324_1%
2
Q17 HUF76129D3S 0
LOAD CURRENT TP16 R22 46.4k_1% R23 402_1%
3
SW1 Top Side ON TRANSIENT OFF R24 .100 R25 nopop R26 nopop R27 nopop R28 .100
1
2
Q19 2N7002 0
C63 10uF 0 0
Top Side
0
+5V
C
JP1 VID4 VID3 VID2 VID1 VID0 1 3 5 7 9 2 4 6 8 10 VID4 VID3 VID2 VID1 VID0 0 PGOOD CR1
RED
R29 2.43k 1 R31 2.43k
R30 10k
2
VID CODE
3
4
3
GREEN
Q20 2n7002
2
1
POWER GOOD INDICATOR
0
R32 0.0 VCORE0 VCORE+ 0.0 R33 VOUT
ENABLE
+5V
3
SW2 R34 10k 1 C64 1n OFF ENABLE VR ON
Q21 2n7002
2
B
REMOTE SENSE LINES connect at output caps
0
0
0
ENABLE SIGNAL
FIGURE 7. SCHEMATIC 5
9
Application Note 1077
TABLE 1. BILL OF MATERIALS ITEM 1 2 QTY 1 18 REFERENCE CR1 VALUE Dual LED2 TYPE DIGIKEY 67-1372-1-ND FOOTPRINT smdp_led_gw VOLTAGE* -
C3, C59, C60, C61, C14-C18, Q2, Q6, nopop Q10, Q14, C25-C29, R25, R26, R27, R37, R38, R39, R40, R42, R17 C4 C2 C5, C7, C9, C11, C56, C58, C13 C32, C33, C42, C43 C62 C1, C6, C8, C10, C12 C19, C20, C21, C22, C23, C24 C30, C31, C34-C41, C44, C45 7.4nF 12nF 1F nopop 1F 0.1F 330F 22F
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1 1 7 4 1 4 16 12 14 1 1 2 1 1 1 1 1 1 1 2 3 4 8
Panasonic EEFSE0E331R Panasonic: ECJ3YB0J226M Taiyo Yuden TMK325F106ZH Taiyo Yuden TMK325F106ZH BAV99LT1 BERG 2x5 100MIL Header BURNDY KPA8CTP BURNDY KPA8CTP NEWARK 111-0702-001 RED NEWARK 111-0703-001 BLK DIGIKEY 1514-2K-ND DIGIKEY 1514-2K-ND DIGIKEY 1514-2K-ND Panasonic PCC-M104L Series -
0805 0805 1210 1206 0805 7343 1206 1210 1812 0805 SOT23 jumper10 kpa8ctp kpa8ctp pad-170 pad-170 tp-150c100p tp-150c100p tp-150c100p pcc-nx1_nx2_j pwrpak_so8_single pwrpak_so8_single TO-252AA SOT23 0603 0603 0603 0603 0603 0603 0603 0603
10V 16V 10V 16V 10V 6.3V 25V 25V 10V -
C46, C47, C48, C49, C50, C51, C52, 10F C53, C54, C55, C57, C65, C66, C67 C63 C64 D1, D2 JP1 J1 J2 J3 J4 J5 J6 J7, J8 L1, L2, L3, L4 Q1, Q5, Q9, Q13 Q3, Q4, Q7, Q8, Q11, Q12, Q15 Q16 10F 1n BAV99LT1 Jumper - 5Pos VOUT GND +VDC GND +5V +12V GND 0.56H IRF7811W SI4362 HUF76129D3S 2N7002 90K 10K 107K 2.5K 2.43K 710 20 603 10
26 27 28 29 30 31 32 33 34 35 36
2 3 1 4 1 1 1 1 1 1 1
Q18, Q17 Q19, Q20, Q21 R1 R2, R30, R34, R36 R3 R4 R5 R6 R7 R8 R9
10
Application Note 1077
TABLE 1. BILL OF MATERIALS (Continued) ITEM 37 38 39 40 41 42 43 44 45 46 47 QTY 7 3 2 2 1 1 2 2 1 1 10 REFERENCE R10, R12, R14, R32, R33, R16, R35, 0.0 R41 R11, R13, R15 R18, R20 R19, R21 R22 R23 R24, R28 R29, R31 SW1 SW2 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP13, TP14 48 49 50 51 52 53 54 55 56 1 1 1 1 1 1 1 4 1 TP9 TP10 TP11 TP12 TP15 TP16 U1 U2, U3, U4, U5 U6 820PTC 357_1% 324_1% 46.4K_1% 402_1% 0.1 2.43K SPDT DPST Test Point Phase1 Phase2 Phase3 Phase4 VCC_CORE Load Current ISL6244CR ISL6207 HIP2100 C&K SMT DIGIKEY PN CKN1101CT-ND C&K SMT DIGIKEY PN CKN1099CT-ND KEYSTONE 5002 TEK 131-4244-00 TEK 131-4244-00 TEK 131-4244-00 TEK 131-4244-00 TEK 131-4244-00 TEK 131-4244-00 Intersil ISL6244 Intersil ISL6207 Intersil HIP2100 VALUE Vishay TFPT0805L820F Vishay WSL series TYPE FOOTPRINT 0603 0805 0603 0603 0603 0603 2512 0603 gt11sc gt11sc PAD-100 TEK 131-4244-00 TEK 131-4244-00 TEK 131-4244-00 TEK 131-4244-00 TEK 131-4244-00 TEK 131-4244-00 32mlfp_5x5 soic8 soic8 VOLTAGE* -
11
Application Note 1077
TOP LAYER SILKSCREEN
12
Application Note 1077
LAYER 2
13
Application Note 1077
LAYER 3
14
Application Note 1077
LAYER 4
15
Application Note 1077
BOTTOM SILKSCREEN
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 16

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